In the related art, high performance of a semiconductor device has been achieved through miniaturization of the semiconductor itself, but reached the limit in terms of physical limitation, an increase of cost, and power consumption. As an alternative technology, a three-dimensional mounting structure which achieves high performance of a device without performing miniaturization by stacking a plurality of thinned semiconductors is practically used as, for example, memory or a CMOS image sensor (CIS).
Related technologies are disclosed in, for example, Japanese Laid-Open Patent Publication Nos. 2007-234725 and 2001-094039.